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| PI6C48533-01 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer Features * * * * * * * * * * * * Pin-to-pin compatible to ICS8533-01 Maximum operation frequency: 800MHz 4 pair of differential LVPECL outputs Selectable differential CLK and PCLK inputs CLK, nCLK pair accepts LVDS, LVPECL, LVHSTL, SSTL and HCSL input level PCLK, nPCLK pair supports LVPECL, CML and SSTL input level Output Skew: 100ps (maximum) Part-to-part skew: 150ps (maximum) Propagation delay: 2ns (maximum) 3.3V power supply Operating Temperature: -40oC to 85oC Packaging (Pb-free & Green avaliable): -20-pin TSSOP (L) Description The PI6C48533-01 is a high-performance low-skew LVPECL fanout buffer. PI6C48533-01 features two selectable differential inputs and translates to four LVPECL ultra-low jitter outputs. The inputs can also be configured to single-ended with external resistor bias circuit. The CLK input accepts LPECL or LVDS or LVHSTL or SSTL or HCSL signals, and PCLK input accepts LVPECL or SSTL or CML signals. The outputs are synchronized with input clock during asynchronous assertion/deassertion of CLK_EN pin. PI6C48533-01 is ideal for differential to LVPECL translations and/or LVPECL clock distribution. Typical clock translation and distribution applications are data-communications and telecommunications. Block Diagram CLK_EN D LE nCLK Pin Diagram VEE CLK_EN CLK_SEL CLK 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q Q0 nQ0 VCC Q1 nQ1 CLK 0 1 PCLK nPCLK Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 nCLK PCLK nPCLK Q2 nQ2 NC NC VCC VCC Q3 nQ3 CLK_SEL 1 PS8737B 02/08/06 PI6C48533-01 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer Pin Description Name VEE CLK_EN CLK_ SEL CLK nCLK Pin # 1 2 3 4 5 6 7 8, 9 10, 13, 18 11, 12 14, 15 16, 17 19, 20 Type P I_PU I_PD I_PD I_PU I_PD I_PU P O O O O Connect to Negative power supply Description Synchronizing clock enable. When high, clock outputs follow clock input. When low, Qx outputs are forced low, nQx outputs are forced high. LVCMOS/LVTTL level with 50K pull-up. Clock select input. When high, selects PCLK input. When low, selects CLK input. LVCMOS/ LVTTL level with 50K pull-down. Non-inverting differential clock input Inverting differential clock input Non-inverting differential clock input Inverting differential clock input Not connected Connect to 3.3V. Differential output pair, LVPECL interface level. Differential output pair, LVPECL interface level. Differential output pair, LVPECL interface level. Differential output pair, LVPECL interface level. PCLK nPCLK NC VCC Q3, nQ3 Q2, nQ2 Q1, nQ1 Q0, nQ Note: 1. I = Input, O = Output, P = Power supply connection, I_PD = Input with pull down, I_PU = Input with pull up Pin Characteristics Symbol CIN R_pullup R_pulldown Parameter Input Capacitance Input Pullup Resistance Input Pulldown Resistance 50 50 Conditions Min. Typ. Max. 4 Units pF K Control Input Function Table(1) Inputs CLK_EN 0 0 1 1 Note: 1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show below. Outputs Selected Source CLK, nCLK PCLK, nPCLK CLK, nCLK PCLK, nPCLK Q0:Q3 Diasbled: Low Disabled: Low Enabled Enabled nQ0:nQ3 CLK_SEL 0 1 0 1 Diasbled: High Disabled: High Enabled Enabled 2 PS8737B 02/08/06 PI6C48533-01 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer Figure 1. CLK_EN Timing Diagram Disabled nCLK, nPCLK CLK, PCLK CLK_EN Enabled nQ0:nQ3 Q0:Q3 Clock Input Function Table Inputs CLK or PCLK 0 1 0 1 Vcc/2 VCC/2 nCLK Outputs or nPCLK 1 0 Q0:Q3 LOW HIGH LOW HIGH HIGH LOW nQ0:nQ3 Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity None Inverting None Inverting None Inverting None Inverting Inverting Inverting HIGH LOW HIGH LOW LOW HIGH Biased; VIN = VCC/2 Biased; VIN = VCC/2 0 1 Absolute Maximum Ratings(1) Symbol VCC VIN VOUT TSTG Parameter Supply voltage Input voltage Output voltage Storage temperature Conditions Referenced to GND Referenced to GND Referenced to GND -0.5 -0.5 -65 Min. Typ. Max. 4.6 VCC+0.5V VCC+0.5V 150 V oC Units Note: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress speci fications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 3 PS8737B 02/08/06 PI6C48533-01 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer Operating Conditions Symbol VCC TA IEE Parameter Power Supply Voltage Ambient Temperature Power Supply Current 500 MHz Conditions Min. 3.0 -40 Typ. 3.3 Max. 3.6 85 60 Units V oC mA LVCMOS/LVTTL DC Characteristics (TA = -40oC to 85oC, VCC = 3.0V to 3.6V unless otherwise stated.) Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK, CLK_SEL CLK_EN CLK, CLK_SEL CLK_EN VIN = VCC = 3.6V VIN = VCC = 3.6V VIN = 0V, VCC = 3.6V VIN = 0V, VCC = 3.6V -5 -150 Conditions Min. 2 -0.3 Typ. Max. VCC+0.3 0.8 150 5 A Units V Differential DC Input Characteristics (TA = -40oC to 85oC, VCC = 3.0V to 3.6V unless otherwise stated.) Symbol IIH IIL VPP VCMR Input High Current Input Low Current Parameter nCLK, nPCLK Conditions VIN = VCC = 3.6V VIN = VCC = 3.6V VCC = 3.6V, VIN = 0V VCC = 3.6V, VIN = 0V Min. Typ. Max. 5 150 Units uA uA uA uA CLK, PCLK nCLK, nPCLK -150 -5 0.15 VEE+0.5 1.3 VCC0.85V CLK, PCLK Peak-to-peak Voltage Common Mode Input Voltage(1, 2) V V Notes: 1. For single ended applications, the maximum input voltage for CLK and nCLK is VCC+0.3V 2. Common mode voltage is defined as VIH. 4 PS8737B 02/08/06 PI6C48533-01 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer LVPECL DC Characteristics Symbol IIH IIL VPP VCMR VOH VOL VSWING Input High Current Input Low Current (TA = -40oC to 85oC, VCC = 3.0V to 3.6V, RL= 50 to VCC - 2V, unless otherwise stated below.) Parameter nCLK, nPCLK Conditions VIN = VCC = 3.6V VIN = VCC = 3.6V VCC = 3.6V, VIN = 0V VCC = 3.6V, VIN = 0V Min. Typ. Max. 5 150 Units CLK, PCLK nCLK, nPCLK -150 -5 0.3 VEE+1.5 VCC-1.4 VCC-2.0 0.6 1 VCC VCC-0.9 VCC-1.6 1.0 A CLK, PCLK Peak-to-peak Voltage Common Mode Input Voltage; Note(1,2) Output High Voltage Output Low Voltage Peak-to-peak Output Voltage Swing V Notes: 1. For single ended applications, the maximum input voltage for PCLK and nPCLK is VCC+0.3V. 2. Common mode voltage is defined as VIH. AC Characteristics(1) (TA = -40oC to 85oC, VCC = 3.0V to 3.6V, RL= 50 to VCC - 2V, unless otherwise stated below.) Symbol fmax tPd Tsk(o) Tsk(pp) tr/tf odc Parameter Output Frequency Propagation Part-to-part Delay(2) Skew(3) 20% - 80% 75 40 Skew(4) 1.0 Output-to-output Conditions Min. Typ. 500 Max. 800 2.0 100 150 300 60 % ps Units MHz ns Output Rise/Fall time Output duty cycle Notes: 1. All parameters are measured at 500MHz unless noted otherwise 2. Measured from the VCC/2 of the input to the differential output crossing point 3 Defined as skew between outputs at the same supply voltage and with equal load condition. Measured at the outputs differential crossing point. 4. Defined as skew between outputs on different parts operating at the same supply voltage and with equal load condition. Measured at the outputs differential crossing point. 5 PS8737B 02/08/06 PI6C48533-01 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer Applications Information Wiring the differenctial input to accept single ended levels Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R1/R2 = 0.609. VDD Single Ended Clock Input R1 1K CLK1 nCLK1 C1 0.1 R2 1K Figure 2: Single-ended Signal Driving Differential Input 6 PS8737B 02/08/06 PI6C48533-01 3.3V Low Skew 1-to-4 Differential/LVCMOS to LVPECL Fanout Buffer Packaging Mechanical: 20-Pin TSSOP (L) Ordering Information(1,2) Ordering Code PI6C48533-01LE Package Code L Package Description Pb-free & Green 20-pin 173-mil wide TSSOP Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free and Green Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com 7 PS8737B 02/08/06 |
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